This invention relates to packet-based communication systems such as xe2x80x98Ethernetxe2x80x99 systems wherein user data and other information is conveyed from station to station by means of data packets that in typical form comprise a preamble, address and control data, packet data and a frame check sequence
The invention particularly relates to network devices which comprise some means for storage of packets received by the individual receive ports, a central or common memory into which all packets which are to be transmitted from the device are stored before they are transmitted, a plurality of transmit ports and some means for the temporary storage of packets read out from the common or central memory before they are dispatched from the transmit ports. Such a device may take a variety of forms but the generic term xe2x80x98switchxe2x80x99 is used herein to include hot merely switches in the narrow sense of a layer 2 interconnection device, but also other devices more commonly known as bridges, routers and repeaters so far as the provision of a central or common memory may be necessary or appropriate for use in such devices. It will be understood by those skilled in the art that although the foregoing, indicates both a plurality of receive ports and a plurality of transmit ports, it is common practice to provide a multiplicity of ports that can operate in a duplex manner, being capable of both reception and transmission and accordingly the terms xe2x80x98receivexe2x80x99 port and xe2x80x98transmitxe2x80x99 port are intended to include the receive and transmit functions respectively of ports that are capable of both transmission and reception.
Switches of this general character commonly include at the receive side a switching asic and associated storage, for example in the form of look-up tables which perform an examination of address data in received packets to build up a database of source addresses and to match destination addresses if possible with stored addresses in order to determine which port or ports should be employed for forwarding a received packet.
In modern systems, the demand for performance is often on the limit of what technology can provide. In packets with systems of this general nature, it is quite possible for the central common memory to be unable to accommodate the demands of traffic flow imposed by the stations connected to the switch in which that central memory is located. Two broad categories of memory failure in the sense are known, namely xe2x80x98overrunxe2x80x99 and xe2x80x98underrunxe2x80x99.
A central common memory of the kind normally employed in switches is typically a dynamic random access memory which is organised as a multiplicity of buffer stores, identifiable in known manner by address signals provided by a memory controller. Normally, a buffer is not dedicated to any particular port but is allotted to receive data from the ports promiscuously under the control of the memory controller. Packets from the temporary storage space are read into a selected buffer or chain of buffers under the control of the memory controller and, when the data packets have been read out of that buffer or buffers, the said buffer or buffers return to a xe2x80x98free poolxe2x80x99 and are available for the storage of data packets from any of the ports. However, the invention is not limited to central common memories which are organised in that particular manner.
It is preferable to write packet data to the central memory and to read packet data from in bursts, which are preferably of a fixed size such as 128 bytes, in order to use the available bandwidth efficiently. However, the writing or reading of each burst has to be preceded by a respective xe2x80x98requestxe2x80x99 to the central memory.
A condition of xe2x80x98overrunxe2x80x99 arises when a central common memory becomes oversubscribed, receiving more requests that it can accommodate such as when several sources attempt to obtain access simultaneously to the same block of memory. In the xe2x80x98overrunxe2x80x99 condition, the temporary memory for an individual receive port will (for example) fill up because the data in that temporary memory cannot be passed to the common central memory quickly enough
The other condition, known as xe2x80x98underrunxe2x80x99 is used to denote the condition in which a transmit port commences the transmission of a packet but all the data for that packet cannot be read from the central memory quickly enough. If for example, owing to the existence of multiple requests to the central memory, the latencies associated with reading out a succession of bursts to a particular transmit FIFO may be significantly different and the result is likely to be a gap in the transmission of the packet.
Both overrun and underrun are likely to occur when the burst size is smaller than the average packet size.
The transmission of a packet in an Ethernet switch includes, as indicated above, a frame check sequence which indicates if the packet has been corrupted. Once transmission of a packet has started, if an underrun occurs, causing a break in the data, the packet will be corrupted and therefore be transmitted with a frame sequence check error. One object of the present invention is to avoid erroneous packets being transmitted by virtue of the occurrence of underrun in a common central memory.
This invention is broadly based on the employment of two levels of priority for read requests for data bursts from a common central memory. More particularly, a first priority is preferably a low priority request made at the beginning of a packet. Such a request would have normally the lowest priority with respect to the central memory. The second request is a high priority request, which preferably has a higher priority that the receive ports and is preferably asserted for all transmit bursts from memory after the first.
The provision of a low priority request at the beginning of a packet will avoid or help to avoid the problem of over subscription of the central.
The provision of a second request with a higher priority means that as soon as transmission of a packet has begun it is less likely to be subject to data corruption due to underrun However, too many high priority requests would cause the receive temporary storage to overrun According to a further aspect of the invention, each transmit port may issue only a limited number of high priority requests before transmission of the current packet has finished. The next request from the port will be a low priority request for the start of the next packet. Thereby any backlog which may have built up in the receive temporary storage while the high priority read requests were being serviced can now be cleared before transmission of the next transmit packet occurs. An overrun on the receive side may thereby be prevented.
As indicated previously, the transmission of a packet in an Ethernet switch has several parts, the first part being an inter-packet gap (IPG) which is a compulsory quite time on the transmission link, for example the wire. The packet commences with a preamble, followed by address data and packet data and finally the frame check sequence. If the start of the packet is delayed, the inter-packet gap will increase. This means that packets will not be transmitted at their fastest rate though the advantage is the packets are less likely to be corrupted.